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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC92501/D MC92501 Advance Information ATM Cell Processor The MC92501 is an Asynchronous Transfer Mode (ATM) Cell Processor layer device composed of dedicated high-performance ingress and egress cell processors combined with UTOPIA Level 2-compliant physical (PHY) and UTOPIA Level 1-compliant switch interface (see Figure 1). It integrates address translation, UPC/NPC, OAM, and statistical functions into a single semiconductor device. This second generation ATM cell processor in Motorola' MC92500 series can be used both in the line cards used by the s switching systems in the ATM network core and in the access multiplexer. The primary function of the MC92501 in either application is to provide ATM-layer cell processing and routing functions. The advanced ATM functionality permits simultaneous tranmission of voice, video, and data within broadband services such as high-speed Internet operations, LAN interconnections for commuters, and video-on-demand using a variety of applications such as Digital Subscriber Line Access Multiplexers (DSLAMs), Wide-Area Networks (WANs), Enterprise Switches, and Multi-service Platforms, Ingress PHY Interface Multiple PHY support UTOPIA I/F Ingress Cell Processing VP and VC Address compression NPC/UPC Cell Counting OAM Operations Add Switch parameters Microprocessor Cell Insertion Microprocessor Cell Copying Ingress SWT Interface Independent clock UTOPIA I/F Microprocessor Interface Cell Insertion Cell Extraction Configuration Regs. Maintenance Access Internal Scan External Memory Interface Egress Cell Processing Multicast Translation FMC Generation UTOPIA I/F Egress PHY Interface Multiple PHY support UPC/NPC Cell Counting OAM Operations Address translation Microprocessor Cell Insertion Microprocessor Cell Copying Egress SWT Interface Independent clock Extract overhead UTOPIA I/F Figure 1. MC92501 Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. Rev. 2, Feb. 1999 Preliminary Data (c) 1998, 1999 MOTOROLA, INC. MC92501 Table of Contents ATM Cell Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii For Technical Assistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Data Sheet Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v Section 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Ingress PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Egress PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PLL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 External Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Ingress Switch Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Egress Switch Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Signal Descriptions . . . . . . . . . . . . . . . . . . . .1-1 Section 2 Signal and Packaging Information . . . . . . . .2-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 GTBGA Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 GTBGA Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PHY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Switch Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Section 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . .3-1 Section 4 4.1 4.2 Test Information . . . . . . . . . . . . . . . . . . . . . .4-1 Ordering Information . . . . . . . . . . . . . . . . . . .5-1 Section 5 ii MC92501 Data Sheet MOTOROLA MC92501 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: 1-800-521-6274 TBD http://www.mot.com/SPS/MCTG/MDAD/atmc Data Sheet Conventions This data sheet uses the following conventions: OVERBAR asserted deasserted Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL Values for V IL, VOL, VIH, and V OH are defined by individual product specifications. MOTOROLA MC92501 Data Sheet iii MC92501 New Features in the MC92501 * Implements ATM Layer functions for Broadband ISDN according to ANSI recommendations, ATM Forum UNI 4.0 and TM 4.0 Specifications, ITU recommendations, and Bellcore recommendations. * Provides ABR Relative Rate marking and EFCI marking according to TM 4.0 * Select Discard CLP = 1 (or CLP = 0 + 1) Flow on selected connections * UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface * Supports both Partial Packet Discard (PPD) and Early Packet Discard (EPD) * Change ABR RM Cell priority * Supports CLP transparency * Unidirectional (Ingress or Egress) UPC or NPC Standard ATMC Features in the MC92500 Family * Full duplex operation at data rates up to 155 Mbps * Performs internal VPI and VCI address compression for up to 64 K VCs * CLP-Aware peak, average, and burst-length policing with programmable Tag/ Drop action per policer * Supports up to 16 physical links unsing dedicated Ingress/Egress multiPHY control signals * Each physical link can be configured as either a UNI or NNI port * Supports multicast, multiport address translation * Maintains both virtual connection and physical link counters on both Ingress and Egress cell flows * Provides a flexible 32-bit external memory port for context management * Automated AIS, RDI, CC, and loopback functions with performance monitoring block test on all 64 K connections * Programmable 32-bit microprocessor interface supporting Big-Endian or LittleEndian bus formats * Unidirectional (Ingress only) UPC or NPC design with up to four leaky buckets per connection * Supports a programmable number of additional switch overhead parameters allowing adaptiation to any switch routing header format * Provides per-link cell counters in both directions iv MC92501 Data Sheet MOTOROLA MC92501 Product Documentation The three documents listed in the following table are required for complete description of the MC92501 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): * * * * A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1. MC92501 Documentation Name MC92501 Product Brief MC92501 Technical Data MC92501 User' Manual s ATM Cell Processor Evaluation Board User' Manual s Description MC92501 product overview MC92501 features list and physical, electrical, timing, and package specifications Detailed functional description of the MC92501 configuration, operation, and register programming Detailed description of the ATMC EVB hardware, operation, installation, and design recommendations Order Number MC92501/P MC92501/D MC92501UM/D MC92501EVKUM/D MOTOROLA MC92501 Data Sheet v MC92501 vi MC92501 Data Sheet MOTOROLA 1 Signal Descriptions 1.1 Signal Groupings The input and output signals of the MC92501 are organized into functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1. The MC92501 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special note for this feature is added to the signal descriptions of those inputs. Table 1-1. MC92501 Functional Signal Groupings Functional Group Power (VDD and AVDD) and Ground (VSS and AVSS) Control Processor Interface Ingress PHY Interface Egress PHY Interface PLL External Memory Interface Ingress Switch Interface Egress Switch Interface JTAG Interface Number of Signals 47 4 68 17 18 4 64 13 13 5 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 MOTOROLA MC92501 Data Sheet 1-1 MC92501 VDD ACLK TESTSEL TESTOUT VCOCTL POWER AVDD VSS AVSS PLL ARST EMDATA0-EMDATA31 EMADD2-EMADD23 EMWR EMBSH0-EMBSH3 CONTROL AMODE0-AMODE1 ENID MCLK MADD2-MADD25 MWR MSEL MDS EMBSL0-EMBSL3 EACEN SRXDATA0-SRXDATA7 SRXPRTY EXTERNAL MEMORY INTERFACE PROCESSOR INTERFACE MWSH MWSL MDTACK0-MDTACK1 MDATA0-MDATA31 MINT MREQ0 MREQ1 MREQ2 RXDATA0-RXDATA7 RXPRTY MC92501 SRXSOC SRXCLAV SRXENB SRXCLK STXCLAV STXDATA0-STXDATA7 STXPRTY STXSOC STXENB STXCLK INGRESS SWITCH INTERFACE EGRESS SWITCH INTERFACE INGRESS PHY INTERFACE RXSOC RXEMPTY RXENB RXPHYID0-RXPHYID3 RXADDR4 TXFULL TXDATA0-TXDATA7 TXPRTY TCK TMS TDI TRST TDO JTAG INTERFACE EGRESS INTERFACE PHY TXSOC TXENB TXCCLR TXPHYID0-TXPHYID3 TXPHYIDV NOTE: There are also three N/C (no connect) pins. Figure 1-1. Functional Signal Groups 1-2 MC92501 Data Sheet MOTOROLA MC92501 1.2 Power and Ground Signals Table 1-2. Power and Ground Signals Signal Name VDD AVDD VSS AVSS Input Power Description PLL Analog Power-- Isolate this input to eliminate coupling of digital switching noise into the PLL System Ground PLL Analog Ground-- Isolate this input to eliminate coupling of digital switching noise into the PLL 1.3 Control Signals Table 1-3. Control Signals Signal Name ARST Signal Type Input Detailed Description ATMC Power-up Reset-- This input signal is used for power-up reset of the entire chip. It must be asserted for at least the time required by the PLL to stabilize. ATMC Mode-- These input signals determine the operating mode of the chip' test features. In normal usage these pins should be s grounded. Enable IDD-- This input pin is used for test purposes. In normal usage the ENID pin must be grounded. AMODE0- AMODE1 ENID Note: Input Input All inputs are 5 V tolerant. MOTOROLA MC92501 Data Sheet 1-3 MC92501 1.4 Processor Interface Signals Table 1-4. Processor Interface Signals Signal Name MCLK Signal Type Input Detailed Description MP Clock-- This input signal is used as the Microprocessor clock inside the MC92501. This signal drives the microprocessor logic in the MC92501. The duty cycle should be in the range of 40-60%. MP Address Bus-- This input bus contains the address which is used by the microprocessor to define the register being accessed. This bus is used by the MC92501 at the assertion of MSEL and sampled on the falling edge of MCLK. MP Write-- This input signal is used to determine whether the MP is reading from the MC92501 or writing to it. This signal is sampled by the MC92501 on the falling edge of MCLK. The MC92501 drives MDATA when MSEL = 0 and MWR = 1. MP Select-- This input signal is used to determine that the current access to the MC92501 is valid. This signal is sampled by the MC92501 on the falling edge of MCLK. MP Data Select-- This input signal is used to indicate when the data on MDATA is valid during a write access to the MC92501. This signal is sampled by the MC92501 on the falling edge of MCLK. MP Word Write Enable High-- This signal indicates that the high word is being written. During a maintenance write access, the value detected on MWSH/A1 is driven on the appropriate EMBSH signal. During read access EMBSH signal is always asserted. Address 1-- When configured appropriately during a maintenance write access, this signal serves as Address 1. During a read access, this signal is ignored. Note: This input signal is programmed by the Word Select Signals Mode (WSSM) bit in the Microprocessor Configuration Register (MPCONR). The signal is sampled by the MC92501 on the falling edge of MCLK. Table 1-5 describes the combined MWSH/A1 and MWSL/Size functionality MP Word Write Enable Low-- This signal indicates that the high word is being written. During a maintenance write access, the value detected on MWSL/SIZE is driven on the appropriate EMBSL signal. During read access EMBSL signal is always asserted. Access Size-- When configured appropriately during a maintenance write access, this signal indicates the size of the maintenance write access: either 32 bits or 16 bits access. During a read access, this signal is ignored and the access width is 32 bits. Note: This input signal is programmed by the Word Select Signals Mode (WSSM) bit in the Microprocessor Configuration Register (MPCONR). The signal is sampled by the MC92501 on the falling edge of MCLK. Table 1-5 describes the combined MWSH/A1 and MWSL/Size functionality MADD2- MADD25 Input MWR Input MSEL Input MDS Input MWSH Input A1 Input MWSL Input SIZE Input 1-4 MC92501 Data Sheet MOTOROLA MC92501 Table 1-4. Processor Interface Signals (Continued) Signal Name MDTACK0- MDTACK1 Signal Type Output Detailed Description MP Data Acknowledge 0-1-- These tri-statable output signals are used to indicate the end of an access from the MC92501. At the end of each access, this signal is actively pulled up and then released. The user may program the MC92501 not to drive this signal during certain types of accesses. This signal is output asynchronously to MCLK. MP Data Bus-- This tri-state bidirectional bus provides the general data path between the MC92501 and the microprocessor. MP Interrupt-- This output signal is used to notify the microprocessor of the occurrence of interrupting events. This signal is asserted on the rising edge of ACLK (asynchronous with respect to MCLK). MP Request 0-- This output signal can be programmed to one of three options (described below in note 2). Its default value is option #1: MP Cell In Request (MCIREQ). MP Request 1-- This output signal can be programmed to one of three options (described below in note 2). Its default value is option #2: MP Cell Out Request (MCOREQ).. MP Request 2-- This output signal can be programmed to one of of three options (described below in note 2). Its default value is option #3: External Memory Maintenance Request (EMMREQ). MDATA0- MDATA31 MINT Input/Output Output MREQ0 Output MREQ1 Output MREQ2 Output Notes: 1. 2. All inputs are 5 V tolerant. MREQ0, MREQ1 and MREQ2 signals are fully backward compatible to the MC92501 Revision A MCIREQ, MCOREQ and EMMREQ signals, respectively. The MREQ[n] signals are used by DMA devices and can be programmed to support DMA requests as follows: -- MP Cell In Request: MREQ[n] is an output signal that can be used by an external DMA device as a control line indicating when to start a new cell insertion cycle into the MC92501. It is asserted whenever the Cell Insertion Register array is available to be written. This signal is output on the falling edge of MCLK. -- MP Cell Out Request: MREQ[n] is an output signal may be used by an external DMA device as a control line indicating when to start a new cell extraction cycle from the MC92501. It is asserted whenever the Cell Extraction Register array is available to be read. It is output on the falling edge of MCLK. -- External Memory Maintenance Request: MREQ[n] is an output signal is asserted a programmable number of clock cycles before the start of an External Memory maintenance cycle. It is deasserted after a programmable number of maintenance accesses have been performed. It is output on the falling edge of MCLK. MOTOROLA MC92501 Data Sheet 1-5 MC92501 : Table 1-5. Host Interface Fields WSSM = 0 MWSH 0 0 1 Note: WSSM = 1 and DO-Data Order = 0 A1 x 0 1 WSSM = 1 and DO-Data Order=1 A1 x 1 0 Function MWSL 0 1 0 Size 0 1 1 Size 0 1 1 Write D(31:0) Write D(31:16) Write D(15:00) All Cell Extraction Register, Cell Insertion Register, and General Register accesses are longword (32-bit) accesses, so both MWSH/A1 and MWSL/SIZE should be asserted low for these write accesses when write-enable mode is selected. 1.5 Ingress PHY Interface Signals Table 1-6. Ingress PHY Interface Signals Signal Name RXDATA0- RXDATA7 RXPRTY Signal Type Input Input Detailed Description Receive Data Bus-- This input data bus receives octets from the PHY chip. When RXENB is active, RXDATA is sampled into the MC92501. Receive Data Bus Parity (RXPRTY)-- This input is the odd parity over RXDATA. This input is ignored if RXENB is not active or the parity check is disabled. Receive Start Of Cell (RXSOC)-- This input, when high, indicates that the current RXDATA is the first byte of a cell. This input is sampled when RXENB is active. Receive PHY Empty-- This input, when low, indicates that currently the PHY chip has no available data. Receive Enable-- This output, when low, indicates that the MC92501 is ready to receive data. Receive PHY Device ID Bus 0-3-- In UTOPIA level 1, this is an input bus that indicates the ID number of the PHY device currently transferring data to the MC92501. If only a single PHY device is supported, this bus should be tied low. This bus is sampled along with the first octet of each cell. Receive Address 0-3-- In UTOPIA Level 2, this is an output bus that indicates the 4 least significant bits of the ID number of the PHY device which is being polled or selected by the MC92501. Receive Address 4-- This signal is an output signal that indicates the most significant bit of the ID number of the PHY device that is being polled or selected by the MC92501. RXSOC Input RXEMPTY RXENB RXPHYID0- RXPHYID3 Input Output Input RXADDR0- RXADDR3 RXADDR4 Output Output Note: All inputs are 5 V tolerant. 1-6 MC92501 Data Sheet MOTOROLA MC92501 1.6 Egress PHY Interface Signals Table 1-7. Egress PHY Interface Signals Signal Name TXFULL TXDATA0- TXDATA7 TXPRTY Signal Type Input Output Detailed Description Transmit PHY Full-- This input signal indicates, when low, that the PHY device is full. Transmit Data Bus-- This output data bus transmits octets to the PHY chip. When TXENB is active, TXDATA contains a valid octet for the PHY. Transmit Data Bus Parity-- This output signal is the odd parity over TXDATA. When TXENB is active, TXPRTY is a valid parity bit for the PHY. Transmit Start Of Cell-- This output signal indicates, when high, that the current data on TXDATA is the first byte of a cell. TXSOC is valid when TXENB is asserted. Transmit Enable-- This output signal, when low, indicates that TXDATA, TXPRTY, and TXSOC are valid data for the PHY. Transmit Cell Clear-- This input signal indicates, when low, that the current cell should be cleared from the Egress PHY interface. Transmit PHY ID 0-3-- In UTOPIA level 1, this is an output bus that indicates the ID number of the PHY device to which either the current cell or the next cell is directed. The functionality is controlled by the MC92501 General Configuration Register (GCR). Transmit Address 0-3-- In UTOPIA level 2, this is an output bus that indicates the 4 least significant bits of the ID number of the PHY device which is being polled or selected by the MC92501. Transmit Next PHY ID Valid-- In UTOPIA level 1, this is an output signal that, when low, indicates that TXPHYID (when configured as the next cell' ID) is valid. If TXPHYID is configured to refer to the current s cell, TXPHYIDV is not used. Transmit Address 4-- In UTOPIA level 2, this an output signal that indicates the most significant bit of the ID number of the PHY device which is being polled or selected by the MC92501. Output TXSOC Output TXENB TXCCLR TXPHYID0- TXPHYID3 Output Input Output TXADDR0-- TXADDR3 TXPHYIDV Output Output TXADDR4 Output Note: All inputs are 5 V tolerant. MOTOROLA MC92501 Data Sheet 1-7 MC92501 1.7 PLL Signals Table 1-8. PLL Signals Signal Name ACLK Signal Type Input Detailed Description ATMC Master Clock-- This input signal is used by the PLL to generate the internal master clock of MC92501. The duty cycle should be in the range of 40-60%. This is a dedicated test signal that must be grounded during normal system operation. This is a dedicated test signal that must be connected to the analog ground (AVSS) during normal system operation. This is a dedicated test signal that must be connected to the analog ground (AVSS) during normal system operation. TESTSEL TESTOUT VCOCTL Note: Input Input/Output Input/Output All inputs are 5 V tolerant. 1.8 External Memory Interface Signals Table 1-9. External Memory Interface Signals Signal Name EMDATA0- EMDATA31 EMADD2- EMADD23 EMWR Signal Type Input/Output Output Output Detailed Description External Memory Data Bus-- This tri-statable bidirectional bus is the data path between the MC92501 and External Memory. External Memory Address Bus-- This output bus is the general address bus used by the MC92501 to access the External Memory. External Memory Write-- When asserted (low), this output signal indicates that the current cycle to the External Memory is a write cycle. This signal is asserted within the cycle. External Memory Bank Select High-- These output signals are used to select the high word of the appropriate memory bank. One or more of these signals is asserted for each External Memory access according to the value of EMADD. During a maintenance write access from the microprocessor, the value detected on MWSH is driven on the appropriate EMBSH signal. External Memory Bank Select Low-- These output signals are used to select the low word of the appropriate memory bank. One or more of these signals is asserted for each External Memory access according to the value of EMADD. During a maintenance write access from the microprocessor, the value detected on MWSL is driven on the appropriate EMBSL signal. EMBSH0- EMBSH3 Output EMBSL0- EMBSL3 Output 1-8 MC92501 Data Sheet MOTOROLA MC92501 Table 1-9. External Memory Interface Signals (Continued) Signal Name EACEN Signal Type Output Detailed Description External Address Compression Enable-- This output signal is asserted when data is being written to or read from an external address compression device using the External Memory Data Bus. Note: All inputs are 5 V tolerant. 1.9 Ingress Switch Interface Signals Table 1-10. Ingress Switch Interface Signals Signal Name SRXDATA0- SRXDATA7 Signal Type Output Detailed Description Receive DATA BUS (SRXDATA0-SRXDATA7)-- This three-state output data bus transmits bytes to the switch. When SRXENB is active, SRXDATA contains valid data for the switch. This bus is updated on the rising edge of SRXCLK. Receive Data Bus Parity-- This three-state output is the parity protection of SRXDATA transmitted to the switch. The type of parity (even/odd) is defined by the Ingress Switch Interface Configuration Register (ISWCR).. Receive Start Of Cell-- This three-state output, when high, indicates that the current data on SRXDATA is the first byte of a cell structure (including the overhead bytes). Receive Switch Cell Available-- This output, when asserted, indicates that the MC92501 has a cell ready to transfer to the switch. When deasserted, it indicates that currently there is no data available for the switch. Receive Enable-- This input, when low, enables new values on SRXDATA, SRXPRTY and SRXSOC. Receive Clock-- This input is used to clock the Ingress switch interface signals. SRXPRTY Output SRXSOC Output SRXCLAV Output SRXENB SRXCLK Note: Input Input All inputs are 5 V tolerant. MOTOROLA MC92501 Data Sheet 1-9 MC92501 1.10 Egress Switch Interface Signals Table 1-11. Egress Switch Interface Signals Signal Name STXCLAV STXDATA0- STXDATA7 STXPRTY Signal Type Output Input Detailed Description Transmit Cell Available-- This output, when asserted, indicates that the MC92501 is prepared to receive a complete cell. Transmit Data Bus-- This input data bus receives bytes from the switch. When STXENB is asserted, STXDATA is sampled into the MC92501 on the rising edge of STXCLK. Transmit Data Bus Parity-- This input is the parity over STXDATA. The type of parity (even/odd) and the parity check control are defined by the Egress Switch Interface Configuration Register (ESWCR). This input is ignored if STXENB is deasserted or the parity check is disabled. It is sampled on the rising edge of STXCLK. Transmit Start Of Cell-- This input indicates, when high, that the current data is the first byte of a cell structure (including the overhead bytes). This input is sampled on the rising edge of STXCLK when STXENB is asserted. Transmit Enable-- This input, when low, enables STXDATA, STXPRTY, and STXSOC. Transmit Clock-- This input signal is used to clock the Egress switch interface signals. Input STXSOC Input STXENB STXCLK Note: Input Input All inputs are 5 V tolerant. 1.11 JTAG Interface Signals Table 1-12. JTAG Interface Signals Signal Name TCK TMS TDI TRST Signal Type Input Input Input Input Detailed Description Test Clock-- This input pin is the JTAG clock. The TDO, TDI, and TMS pins are synchronized by this signal. Test Mode Select-- This input signal is sampled on the rising edge of TCK. TMS is responsible for the state change in the test access port state machine. Test Data Input-- This input signal is sampled on the rising edge of TCK. TDI is the data to be shifted toward the TDO output. Test Reset-- This input signal is the JTAG asynchronous reset. When asserted low, the Test Access Port is forced to the Test_Logic_Reset state. When JTAG is not being used, this signal should be hard-wired to GND or tied to ARST. Test Data Output-- This tri-state output changes its logical value on the falling edge of TCK. TDO Note: Output All inputs are 5 V tolerant. 1-10 MC92501 Data Sheet MOTOROLA 2 Signal and Packaging Information 2.1 Introduction This section provides information on packaging, including a diagram of the package with signals and tables showing how the signals described in Section 1 are allocated. The MC92501 is available in a 256-lead Glob-Top Ball Grid Array (GTBGA) package. The package mechanical drawing is provided at the end of this section. MOTOROLA MC92501 Data Sheet 2-1 MC92501 2.2 GTBGA Package Description A GTBGA package top view is shown in Figure 2-1 with signal and location designators. 1 A B C D E F G H J K L M N P R T U V W Y VSS 2 ACLK 3 MADD16 4 MADD13 5 MADD9 6 MADD6 7 MADD4 8 MSEL 9 MINT 10 MWSH 11 MWSL 12 SRXDATA7 13 SRXDATA3 14 SRXDATA0 15 SRXSOC 16 RXSOC 17 RXPHYID3 18 RXPHYID2 19 VSS 20 VSS AVSS TESTSEL VSS MADD15 MADD12 MADD8 MADD5 MADD2 MDTACK0 MWR SRXENB SRXDATA6 SRXDATA2 SRXCLK SRXPRTY RXENB RXPRTY VDD VDD RXDATA6 MADD18 AVDD TESTOUT VDD MADD14 MADD11 MADD7 MADD3 MREQ1 MCLK MDS SRXDATA5 SRXDATA1 SRXCLAV RXADDR4 RXEMPTY RXPHYID0 RXDATA7 RXDATA5 RXDATA2 MADD19 VCOCTL VDD VSS MADD17 VDD MADD10 VSS MREQ0 MREQ2 VDD SRXDATA4 VSS MDTACK1 VDD RXPHYID1 VSS RXDATA4 RXDATA1 EMDATA31 MADD22 MADD21 MADD20 VSS RXDATA3 RXDATA0 EMDATA30 EMDATA27 MDATA0 MADD25 MADD23 VDD VDD EMDATA29 EMDATA26 EMDATA24 MDATA3 MDATA2 MDATA1 MADD24 EMDATA28 EMDATA25 EMDATA23 EMDATA22 MDATA6 MDATA5 MDATA4 VSS VSS EMDATA21 EMDATA20 EMDATA19 MDATA10 MDATA9 MDATA8 MDATA7 EACEN EMWR EMDATA18 EMDATA17 MDATA13 MDATA11 MDATA12 VDD EMDATA16 EMDATA15 EMDATA14 EMDATA13 MDATA14 MDATA15 MDATA16 MDATA17 VDD EMDATA11 EMDATA10 EMDATA12 MDATA18 MDATA19 MDATA20 MDATA21 EMDATA6 EMDATA7 EMDATA8 EMDATA9 MDATA22 MDATA23 MDATA24 VSS VSS EMDATA3 EMDATA4 EMDATA5 MDATA25 MDATA26 MDATA28 MDATA31 EMADD22 VDD EMDATA1 EMDATA2 MDATA27 MDATA29 TXPHYID0 VDD VDD EMADD21 EMADD23 EMDATA0 MDATA30 TXPHYID1 TXPHYID3 TXDATA2 EMADD16 VSS EMADD19 EMADD20 TXPHYID2 TXDATA0 TXDATA3 VSS TXPRTY VDD STXDATA1 VSS STXCLAV VDD AMODE1 EMBSL1 VSS EMADD3 VDD EMADD9 VSS EMADD15 EMADD14 EMADD18 TXDATA1 TXDATA4 TXDATA6 TXSOC TXFULL STXDATA0 STXDATA4 STXDATA7 STXCLK TMS AMODE0 EMBSL2 EMBSH3 VDD EMADD4 VSS EMADD10 EMADD13 VDD EMADD17 TXDATA5 VDD VSS TXDATA7 TXENB STXDATA2 STXDATA5 STXPRTY ENID TDO ARST EMBSL3 nc EMBSH1 nc EMADD5 EMADD7 EMADD11 VDD VSS VSS VDD TXPHYIDV TXCCLR STXENB STXDATA3 STXDATA6 STXSOC TDI TRST TCK nc EMBSL0 EMBSH2 EMBSH0 EMADD2 EMADD6 EMADD8 EMADD12 VSS Notes: 1. 2. Locations marked as nc must not be connected. The figure only shows the primary signal name for each lead. For the Ingress and Egress PHY Interface signals, the primary signal names are those used in UTOPIA Level 1. For UTOPIA Level 2, leads A17, A18, C17, and D16 change to RXADDR3, RXADDR2, RXADDR0, and RXADDR1, respectively. Leads R3, T2, T3, U1, and Y3 change to TXADDR0, TXADDR1, TXADDR3, TXADDR2, and TXADDR4, respectively. The Microprocessor signals also have an alternate configuration that changes leads A10 and A11 to signals A1 and SIZE, respectively. Figure 2-1. MC92501 256-Lead GTBGA Diagram (Top View) 2-2 MC92501 Data Sheet MOTOROLA MC92501 Table 2-1. MC92501 256-Lead GTBGA Package Signal List by Location Location A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Signal Name VSS ACLK MADD16 MADD13 MADD9 MADD6 MADD4 MSEL MINT MWSH/A1 MWSL/SIZE SRXDATA7 SRXDATA3 SRXDATA0 SRXSOC RXSOC RXPHYID3/ RXADDR3 RXPHYID2/ RXADDR2 VSS VSS Location B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 Signal Name AVSS TESTSEL VSS MADD15 MADD12 MADD8 MADD5 MADD2 MDTACK0 MWR SRXENB SRXDATA6 SRXDATA2 SRXCLK SRXPRTY RXENB RXPRTY VDD VDD RXDATA6 Location C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Signal Name MADD18 AVDD TESTOUT VDD MADD14 MADD11 MADD7 MADD3 MREQ1 MCLK MDS SRXDATA5 SRXDATA1 SRXCLAV RXADDR4 RXEMPTY RXPHYID0/ RXADDR0 RXDATA7 RXDATA5 RXDATA2 Location D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 Signal Name MADD19 VCOCTL VDD VSS MADD17 VDD MADD10 VSS MREQ0 MREQ2 VDD SRXDATA4 VSS MDTACK1 VDD RXPHYID1/ RXADDR1 VSS RXDATA4 RXDATA1 EMDATA31 MOTOROLA MC92501 Data Sheet 2-3 MC92501 Table 2-1. MC92501 256-Lead GTBGA Package Signal List by Location (Continued) Location E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 Signal Name MADD22 MADD21 MADD20 VSS RXDATA3 RXDATA0 EMDATA30 EMDATA27 MDATA0 MADD25 MADD23 VDD VDD EMDATA29 EMDATA26 EMDATA24 MDATA3 MDATA2 MDATA1 MADD24 EMDATA28 EMDATA25 EMDATA23 EMDATA22 Location H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 Signal Name MDATA6 MDATA5 MDATA4 VSS VSS EMDATA21 EMDATA20 EMDATA19 MDATA10 MDATA9 MDATA8 MDATA7 EACEN EMWR EMDATA18 EMDATA17 MDATA13` MDATA11 MDATA12 VDD EMDATA16 EMDATA15 EMDATA14 EMDATA13 Location L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 Signal Name MDATA14 MDATA15 MDATA16 MDATA17 VDD EMDATA11 EMDATA10 EMDATA12 MDATA18 MDATA19 MDATA20 MDATA21 EMDATA8 EMDATA7 EMDATA8 EMDATA9 MDATA22 MDATA23 MDATA24 VSS VSS EMDATA3 EMDATA4 EMDATA5 Location P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 Signal Name MDATA25 MDATA26 MDATA28 MDATA31 EMADD22 VDD EMDATA1 EMDATA2 MDATA27 MDATA29 TXPHYID0/ TXADDR0 VDD VDD EMADD21 EMADD23 EMDATA0 MDATA30 TXPHYID1/ TXADDR1 TXPHYID3/ TXADDR3 TXDATA2 EMADD16 VSS EMADD19 EMADD20 2-4 MC92501 Data Sheet MOTOROLA MC92501 Table 2-1. MC92501 256-Lead GTBGA Package Signal List by Location (Continued) Location U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 Signal Name TXPHYID2/ TXADDR2 TXDATA0 TXDATA3 VSS TXPRTY VDD STXDATA1 VSS STXCLAV VDD AMODE1 EMBSL1 VSS EMADD3 VDD EMADD9 VSS EMADD15 EMADD14 EMADD18 Location V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Signal Name TXDATA1 TXDATA4 TXDATA6 TXSOC TXFULL STXDATA0 STXDATA4 STXDATA7 STXCLK TMS AMODE0 EMBSL2 EMBSH3 VDD EMADD4 VSS EMADD10 EMADD13 VDD EMADD17 Location W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal Name TXDAT5 VDD VSS TXDATA7 TXENB STXDATA2 STXDATA5 STXPRTY ENID TDO ARST EMBSL3 nc EMBSH1 nc EMADD5 EMADD7 EMADD11 VDD VSS Location Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name VSS VDD TXPHYIDV/ TXADDR4 TXCCLR STXENB STXDATA3 STXDATA6 STXSOC TDI TRST TCK nc EMBSL0 EMBSH2 EMBSH0 EMADD2 EMADD6 EMADD8 EMADD12 VSS MOTOROLA MC92501 Data Sheet 2-5 MC92501 Table 2-2. MC92501 256-Lead GTBGA Package Signal List by Name Signal Name A1 ACLK AMODE0 AMODE1 ARST AVDD AVSS EACEN EMADD10 EMADD11 EMADD12 EMADD13 EMADD14 EMADD15 EMADD16 EMADD17 EMADD18 EMADD19 EMADD2 EMADD20 Location A10 A2 V11 U11 W11 C2 B1 J17 V17 W18 Y19 V18 U19 U18 T17 V20 U20 T19 Y16 T20 Signal Name EMADD21 EMADD22 EMADD23 EMADD3 EMADD4 EMADD5 EMADD6 EMADD7 EMADD8 EMADD9 EMBSH0 EMBSH1 EMBSH2 EMBSH3 EMBSL0 EMBSL1 EMBSL2 EMBSL3 EMDATA0 EMDATA1 Location R18 P17 R19 U14 V15 W16 Y17 W17 Y18 U16 Y15 W14 Y14 V13 Y13 U12 V12 W12 R20 P19 Signal Name EMDATA10 EMDATA11 EMDATA12 EMDATA13 EMDATA14 EMDATA15 EMDATA16 EMDATA17 EMDATA18 EMDATA19 EMDATA2 EMDATA20 EMDATA21 EMDATA22 EMDATA23 EMDATA24 EMDATA25 EMDATA26 EMDATA27 EMDATA28 Location L19 L18 L20 K20 K19 K18 K17 J20 J19 H20 P20 H19 H18 G20 G19 F20 G18 F19 E20 G17 Signal Name EMDATA29 EMDATA3 EMDATA30 EMDATA31 EMDATA4 EMDATA5 EMDATA7 EMDATA8 EMDATA8 EMDATA9 EMWR ENID MADD10 MADD11 MADD12 MADD13 MADD14 MADD15 MADD16 MADD17 Location F18 N18 E19 D20 N19 N20 M18 M17 M19 M20 J18 W9 D7 C6 B5 A4 C5 B4 A3 D5 2-6 MC92501 Data Sheet MOTOROLA MC92501 Table 2-2. MC92501 256-Lead GTBGA Package Signal List by Name (Continued) Signal Name MADD18 MADD19 MADD2 MADD20 MADD21 MADD22 MADD23 MADD24 MADD25 MADD3 MADD4 MADD5 MADD6 MADD7 MADD8 MADD9 MCLK MDATA0 MDATA1 MDATA10 MDATA11 MDATA12 MDATA13 MDATA14 MDATA15 Location C1 D1 B8 E3 E2 E1 F3 G4 F2 C8 A7 B7 A6 C7 B6 A5 C10 F1 G3 J1 K2 K3 K1 L1 L2 Signal Name MDATA16 MDATA17 MDATA18 MDATA19 MDATA2 MDATA20 MDATA21 MDATA22 MDATA23 MDATA24 MDATA25 MDATA26 MDATA27 MDATA28 MDATA29 MDATA3 MDATA30 MDATA31 MDATA4 MDATA5 MDATA6 MDATA7 MDATA8 MDATA9 MDS Location L3 L4 M1 M2 G2 M3 M4 N1 N2 N3 P1 P2 R1 P3 R2 G1 T1 P4 H3 H2 H1 J4 J3 J2 C11 Signal Name MDTACK0 MDTACK1 MINT MREQ0 MREQ1 MREQ2 MSEL MWR MWSH MWSL nc nc nc RXADDR0 RXADDR1 RXADDR2 RXADDR3 RXADDR4 RXDATA0 RXDATA1 RXDATA2 RXDATA3 RXDATA4 RXDATA5 RXDATA6 Location B9 D14 A9 D9 C9 D10 A8 B10 A10 A11 W13 W15 Y12 C17 D16 A18 A17 C15 E18 D19 C20 E17 D18 C19 B20 Signal Name RXDATA7 RXEMPTY RXENB RXPHYID0 RXPHYID1 RXPHYID2 RXPHYID3 RXPRTY RXSOC SIZE SRXCLAV SRXCLK SRXDATA0 SRXDATA1 SRXDATA2 SRXDATA3 SRXDATA4 SRXDATA5 SRXDATA6 SRXDATA7 SRXENB SRXPRTY SRXSOC STXCLAV STXCLK Location C18 C16 B16 C17 D16 A18 A17 B17 A16 A11 C14 B14 A14 C13 B13 A13 D12 C12 B12 A12 B11 B15 A15 U9 V9 MOTOROLA MC92501 Data Sheet 2-7 MC92501 Table 2-2. MC92501 256-Lead GTBGA Package Signal List by Name (Continued) Signal Name STXDATA0 STXDATA1 STXDATA2 STXDATA3 STXDATA4 STXDATA5 STXDATA6 STXDATA7 STXENB STXPRTY STXSOC TCK TDI TDO TESTOUT TESTSEL TMS TRST TXADDR0 TXADDR1 TXADDR2 TXADDR3 Location V6 U7 W6 Y6 V7 W7 Y7 V8 Y5 W8 Y8 Y11 Y9 W10 C3 B2 V10 Y10 R3 T2 U1 T3 Signal Name TXADDR4 TXCCLR TXDAT5 TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA6 TXDATA7 TXENB TXFULL TXPHYID0 TXPHYID1 TXPHYID2 TXPHYID3 TXPHYIDV TXPRTY TXSOC VCOCTL VDD VDD Location Y3 Y4 W1 U2 V1 T4 U3 V2 V3 W4 W5 V5 R3 T2 U1 T3 Y3 U5 V4 D2 B18 B19 Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS Location C4 D11 D15 D3 D6 F17 F4 K4 L17 P18 R17 R4 U10 U15 U6 V14 V19 W19 W2 Y2 A1 A19 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Location A20 B3 D13 D17 D4 D8 E4 H17 H4 N17 N4 T18 U13 U17 U4 U8 V16 W20 W3 Y1 Y20 2-8 MC92501 Data Sheet MOTOROLA MC92501 2.3 GTBGA Mechanical Drawing GC Suffix Case 1208-01 Figure 2-2. Glob-Top Ball Grid Array (GTBGA) Package MOTOROLA MC92501 Data Sheet 2-9 MC92501 2-10 MC92501 Data Sheet MOTOROLA 3 Specifications 3.1 Introduction This section provides the following sets of physical and electrical specifications for the MC92501: * * * * * * * * Absolute Maximum Ratings Recommended Operating Conditions DC Electrical Characteristics Clocks Microprocessor Interface Timing PHY Interface Timing Switch Interface Timing External Memory Interface Timing MOTOROLA MC92501 Data Sheet 3-1 MC92501 3.2 Absolute Maximum Ratings Table 3-1. Absolute Maximum Ratings Symbol VDD VIN2 VOUT2,3 I I TSTG TL Notes: 1. 2. 3. 4. Parameter DC Supply Voltage DC Input Voltage (5 V Tolerant) DC Output Voltage DC Current Drain per Pin, Any Single Input or Output DC Current Drain VDD and VSS Pins Storage Temperature Lead Temperature (10 s soldering) Value/Value Range1 -0.5 to 3.8 -0.5 to 5.8 -0.5 to V DD + 0.5 50 100 -65 to +150 300 Unit V V V mA mA C C Maximum ratings are those values beyond which damage to the device may occur. All input, bidirectional, and MDTACK are 5 V Tolerant. For proper operation it is recommended that Vin and Vout be constrained to 0 < (VIN,V OUT) < 5.5 V. SRXDATAx, SRXSOC, SRXPRTY, TDO tri-state outputs must be constrained to 0 < VOUT < VDD in the high impedance state. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 3.3 Recommended Operating Conditions Table 3-2. Recommended Operating Conditions to Guarantee Functionality Symbol VDD Vin TA Notes: 1. 2. 3. Parameter DC Supply Voltage, VDD = 3.3V (Nominal) Input Voltage (5V Tolerant) Industrial Operating Temperature Min 3.0 0 -40 Max 3.6 5.5 85 Unit V V C All parameters are characterized for DC conditions after thermal equilibrium has been established. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V ss or V DD). This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 3-2 MC92501 Data Sheet MOTOROLA MC92501 3.4 DC Electrical Characteristics Table 3-3. DC Electrical Characteristics Symbol VIH VIL IIN Parameter TTL Inputs (5V Tolerant) TTL Inputs (5V Tolerant) Input Leakage Current, No Pull Resistor With Pullup Resistor * With Pulldown Resistor * Condition -- -- VIN = VDD or VSS Min. 2.2 -0.3 -5 -50 5 Max. 5.5 0.8 5 -5 50 -- Unit V V A IOH Output High Current, LVTTL Output Type Outputs: EACEN, EMWR, EMADDx, EMBSHx, EMBSLx Output High Current, LVTTL Output Type Outputs: All other outputs VDD = Min, VOH Min = 0.8 V DD -24 mA -4 -- IOL Output Low Current, LVTTL Output Type Outputs: EACEN, EMWR, EMADDx, EMBSHx, EMBSLx Output Low Current, LVTTL Output Type Outputs: All other outputs VDD = Min, VOL Max = 0.4 V 24 -- mA 4 -- IOZ IDDQ IDD Output Leakage Current, Tri-State Output Max Quiescent Supply Current Output = High Impedance VOUT = VDD or V SS IOUT = 0 mA VIN = VDD or VSS Nominal Load Capacitance, ACLK = 25.6 Mhz, MCLK = 33 Mhz -- -10 10 3001 10 A A mA Max Dynamic Supply Current CI Notes: 1. 2. 3. 4. Input Capacitance (TTL) -- 8 pF Under Typical Loca, 25 Mhz ACLK/MCLK TA = -40C to 85C, VDD=3.3 V 0.3 V Guaranteed Inputs may be modified to include pullup resistors at any time. See Section 1 for pin input/output type. MOTOROLA MC92501 Data Sheet 3-3 MC92501 3.5 Clocks Table 3-4. Clock Timing Num C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 ACLK Cycle Time ACLK Pulse Width Low ACLK Pulse Width High ACLK Rise/Fall Time MCLK Cycle Time MCLK Pulse Width Low MCLK Pulse Width High MCLK Rise/Fall Time Characteristics Min 39 15 15 -- 30 12 12 -- 30 12 12 -- Max 80 -- -- 5 -- -- -- 5 -- -- -- 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns SRXCLK/STXCLK Cycle Time SRXCLK/STXCLK Pulse Width Low SRXCLK/STXCLK Pulse Width High SRXCLK/STXCLK Rise/Fall Time C1 C3 ACLK C4 C5 C4 C2 C7 MCLK C6 C8 C9 C11 C8 SRXCLK / STXCLK C10 C12 C12 Figure 3-1. Clock Timing Diagrams 3-4 MC92501 Data Sheet MOTOROLA MC92501 3.6 Microprocessor Interface Timing The timing diagrams in this section are intended to convey setup and hold values for input signals and propagation delay values for output signals. For functional timing diagrams, see Section 4.5 Microprocessor Interface. Table 3-5. Microprocessor Interface Timings Num 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 Characteristics MSEL setup time before MCLK falling edge MSEL hold time after MCLK falling edge MADD/MWR setup time before MSEL assertion MADD/MWR hold time after MCLK falling edge1 MDS setup time before MCLK falling edge MDS hold time after MCLK falling edge MDATA setup time before MCLK falling edge MDATA hold time after MCLK falling edge MSEL assertion to MDATA active MCLK falling edge to MDATA valid for CER Accesses 2 MSEL deassertion to MDATA invalid MSEL deassertion to MDATA inactive MWR assertion to MDATA invalid MWR assertion to MDATA inactive MCLK rising edge to MDATA valid for Maintenance Accesses 2,3 MCLK falling edge to MDATA valid for General Register Accesses 2,4 MSEL assertion to MDTACK active MCLK falling edge to MDTACK inactive MSEL assertion to MDTACK0 asserted5 MSEL deassertion to MDTACK deasserted5 MCLK rising edge to MDTACK asserted5 MWSH, MWSL setup time before MCLK falling edge1 MWSH, MWSL hold time after MCLK falling edge1 MCLK falling edge to REQ valid Min 5 1 5 3 5 1 4 1 0 Max Unit ns ns ns ns ns ns ns ns ns 26 1 11 1 11 TD TR 0 12 9 13 13 2 3 0 14 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MOTOROLA MC92501 Data Sheet 3-5 MC92501 Table 3-5. Microprocessor Interface Timings (Continued) Num 27 28 29 Characteristics MCLK falling edge to MDTACK asserted for General Register Read Accesses 5,6 MCLK falling edge to MDTACK asserted for General Register Write Accesses 5,7 Access width (MCLK falling edge to MSEL deassertion) for General Register Write Accesses 8 Min Max TRD TWD Unit ns ns TW 12 0 5 ns ns 30 31 MSEL assertion to MDTACK1 asserted9 MDTACK0 assertion to MDTACK1 assertion Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. This refers only to the first falling edge of MCLK in each access at which MSEL is asserted. This is for a 150 pF load. Add 0.9 ns for each additional 10 pF. For a 100 pF load, subtract 4 ns. TD = External Memory access time + 18 ns TR = 4 * ACLK period + 20 ns This is for a 50 pF load. TRD = 4 * ACLK period + 11 ns TWD is measured from the MCLK falling edge at which MDS is sampled as asserted. TWD = 4 * ACLK period + 11 ns TW is measured from the MCLK falling edge at which MDS is sampled as asserted. TW = 4 * ACLK period. Note that the setup and hold times with respect to MCLK (timing values 1 and 2) still apply. This is for a 50 pF load. 3-6 MC92501 Data Sheet MOTOROLA MC92501 MCLK 1 2 MSEL 3 MADD [25:2] 4 3 MWR 4 15 11 14 13 9 MDATA [31:0] 12 Data Valid 21 19 MDTACK0 22 20 31 MDTACK1 30 Figure 3-2. Cell Extraction Register Read Access Timing MOTOROLA MC92501 Data Sheet 3-7 MC92501 MCLK 1 MSEL 2 3 MADD [25:2] 4 3 MWR 4 15 16 14 13 9 MDATA [31:0] 12 Data Valid 22 19 MDTACK 23 20 Figure 3-3. Maintenance Read Access Timing 3-8 MC92501 Data Sheet MOTOROLA MC92501 MCLK 1 MSEL 2 3 MADD [25:2] 4 3 MWR 4 15 17 14 13 9 MDATA [31:0] 12 Data Valid 27 19 MDTACK 22 20 Figure 3-4. General Register Read Access Timing MOTOROLA MC92501 Data Sheet 3-9 MC92501 MCLK 1 2 MSEL 3 4 MADD [25:2] 3 4 MWR 24 25 MWSH MWSL 5 6 MDS 7 8 MDATA [31:0] Data Valid 21 30 19 22 20 MDTACK Figure 3-5. Cell Insertion Register Write Access/Maintenance Write Access Timing 3-10 MC92501 Data Sheet MOTOROLA MC92501 MCLK 1 MSEL 29 3 MADD [25:2] 4 3 MWR 4 24 MWSH MWSL 25 5 MDS 7 6 8 Data Valid MDATA [31:0] 19 MDTACK 28 Figure 3-6. General Register Write Access Timing MCLK 26 26 MCIREQ, MCOREQ, EMMREQ Figure 3-7. DMA Request Signals Timing MOTOROLA MC92501 Data Sheet 3-11 MC92501 3.7 PHY Interface Timing Table 3-6. PHY Interface Timings Num 51 52 53 Notes: 1. 2. Characteristics Setup time before ACLK rising edge Hold time after ACLK rising edge Propagation delay from rising edge of ACLK1 Min 10 1 1 Max -- -- 16 2 Unit ns ns ns For a 200 pF load. Add 0.25 ns for each additional 10 pF. For 100 pF subtruct 2.5 ns. 16 ns for 70 17 ns for 85 C, C ACLK 51 RXEMPTY RXSOC RXDATA RXPRTY RXPHYID 53 52 RXENB, RXADDR Figure 3-8. Receive PHY Interface Timing ACLK 52 51 TXFULL TXCCLR 53 TXDATA TXPRTY TXSOC TXENB TXPHYID TXNPHYIDV Figure 3-9. Transmit PHY Interface Timing 3-12 MC92501 Data Sheet MOTOROLA MC92501 3.8 Switch Interface Timing Table 3-7. Switch Interface Timing Num 61 62 63 64 65 Characteristics Setup time before SRXCLK/STXCLK rising edge Hold time after SRXCLK/STXCLK rising edge Propagation delay from rising edge of SRXCLK/STXCLK SRXCLK rising edge to outputs active SRXCLK rising edge to outputs inactive Min 4 1 1 1 1 Max Unit ns ns 18 ns 16 SRXCLK 61 SRXENB 62 63 64 SRXSOC SRXDATA SRXPRTY 65 Figure 3-10. Ingress Switch Interface Timing STXCLK 61 STXDATA STXPRTY STXSOC STXENB 62 63 STXCLAV Figure 3-11. Egress Switch Interface Timing MOTOROLA MC92501 Data Sheet 3-13 MC92501 3.9 External Memory Interface Timing This section represents External Memory timing parameters for the default definition of the External Memory Timing Configuration Register (EMTCR). These values are for a load of up to 50 pF, which is the rated maximum load for the External Memory interface pins. 3.9.1 Write Cycle Timing Table 3-8. Write Cycle Timing Num 81 82 83 84 85 87 88 Note: Write Pulse Width Characteristics EMWR assertion time. EMWR low to end of Write. Address Setup Time. EMADD Valid to Beginning of Write. Address Valid Time. During this Time EMADD is Valid. Address Hold Time. End of Write to EMADD Invalid. Data Setup Time. EMDATA Valid to End of Write. Data Hold Time. End of Write to EMDATA Invalid. Min 16 22 6 32 6 13 6 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns A write occurs during the overlap of EMBSH0-3, EMBSL0-3, EACEN low and EMWR low. 3-14 MC92501 Data Sheet MOTOROLA MC92501 81 EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN 82 EMWR 84 83 EMADD [23:2] 85 87 EMDATA [31:0] Data Valid 88 Figure 3-12. External Memory Write Access Timing MOTOROLA MC92501 Data Sheet 3-15 MC92501 3.9.2 Read Cycle Timing Table 3-9. Read Cycle Timing Num 90 92 93 94 95 96 97 Notes: 1. 2. Characteristics Enable Pulse Width. EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN Pulse Width. Address Setup Time. EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN High. Address Hold Time. EMADD Invalid to EMBSH0-EMBSH3, EMBSL0- EMBSL3, EACEN High Data Driving Start Point. EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN Low to EMDATA Active. Data Setup Time. EMDATA Valid to EMBSH0-EMBSH3, EMBSL0- EMBSL3, EACEN High. Data Hold Time. EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN High to EMDATA Invalid. Data Driving End Point. EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN High to EMDATA Inactive2 Min 28 33 -- 0 5 0 -- Max -- -- 11 -- -- -- 9 Unit ns ns ns ns ns ns ns A RAM with hold time from address change to data change is required. Failure to meet this value may result in contention on EMDATA if a write access follows. 3-16 MC92501 Data Sheet MOTOROLA MC92501 90 EMBSH0-EMBSH3, EMBSL0-EMBSL3, EACEN EMWR 93 92 EMADD 97 95 94 EMDATA [31:0] 96 Data Figure 3-13. External Memory Read Access Timing MOTOROLA MC92501 Data Sheet 3-17 MC92501 3-18 MC92501 Data Sheet MOTOROLA 4 Test Information 4.1 Device Identification Register The code for the MC92501 is 0100_0001_1100_0011_1010_0000_0001_1101. 4.2 Boundary Scan Register Table 4-1. MC92501 Boundary Scan Bit Definition Signal Name STXCLK STXCLAV STXSOC STXPRTY STXDATA7 STXDATA6 STXDATA5 STXDATA4 STXDATA3 STXDATA2 STXDATA1 STXDATA0 STXENB TXENB TXFULL TXCCLR I/O Cell Type in bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir in bidir System Mode in out in in in in in in in in in in in out in in 360 359 357 355 353 351 349 347 345 343 341 339 337 335 333 332 Scan Bit # -- 358 356 354 352 350 348 346 344 342 340 338 336 334 -- 331 Output Enable -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOTOROLA MC92501 Data Sheet 4-1 MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name TXPHYIDV TXPRTY TXSOC TXDATA7 TXDATA6 TXDATA5 TXDATA4 TXDATA3 TXDATA2 TXDATA1 TXDATA0 TXPHYID3 TXPHYID2 TXPHYID1 TXPHYID0 MDATA31 MDATA30 MDATA29 MDATA28 MDATA27 MDATA26 MDATA25 MDATA24 MDATA23 MDATA22 MDATA21 MDATA20 MDATA19 MDATA18 I/O Cell Type tri-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir tri-state tri-state tri-state tri-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir System Mode out out out out out out out out out out out out out out out bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir 330 329 327 325 323 321 319 317 315 313 311 309 308 307 306 305 303 301 299 297 295 293 291 289 287 285 283 281 279 Scan Bit # -- 328 326 324 322 320 318 316 314 312 310 -- -- -- -- 304 302 300 298 296 294 292 290 288 286 284 282 280 278 Output Enable -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 4-2 MC92501 Data Sheet MOTOROLA MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name MDATA17 MDATA16 MDATA15 MDATA14 MDATA13 MDATA12 MDATA11 MDATA10 MDATA9 MDATA8 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 MADD25 MADD24 MADD23 MADD22 MADD21 MADD20 MADD19 MADD18 MADD17 MADD16 MADD15 I/O Cell Type bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir System Mode bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir in in in in in in in in in in in 277 275 273 271 269 267 265 263 261 259 257 255 253 251 249 247 245 243 241 239 237 235 233 231 229 227 225 223 221 Scan Bit # 276 274 272 270 268 266 264 262 260 258 256 254 252 250 248 246 244 242 240 238 236 234 232 230 228 226 224 222 220 Output Enable enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 -- -- -- -- -- -- -- -- -- -- -- MOTOROLA MC92501 Data Sheet 4-3 MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name MADD14 MADD13 MADD12 MADD11 MADD10 MADD9 MADD8 MADD7 MADD6 MADD5 MADD4 MADD3 MADD2 MSEL MREQ0 MREQ1 MDTACK0 MINT MREQ2 MCLK MWR MWSH MWSL MDS MDATA19 SRXENB SRXDATA7 SRXDATA6 SRXDATA5 I/O Cell Type bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir in tri-state tri-state tri-state tri-state tri-state in in in in in bid in bidir bidir bidir System Mode in in in in in in in in in in in in in in out out tri-state out out in in in in in 219 217 215 213 211 209 207 205 203 201 199 197 195 193 192 191 190 189 188 187 186 185 184 Scan Bit # 218 216 214 212 210 208 206 204 202 200 198 196 194 -- -- -- enscan2 -- -- -- -- -- -- -- -- Output Enable -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- enscan4 enscan4 enscan4 183can1 in tri-state tri-state tri-state 182 181 179 177 -- 180 178 176 4-4 MC92501 Data Sheet MOTOROLA MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name SRXDATA4 SRXDATA3 SRXDATA2 SRXDATA1 SRXDATA0 SRXCLK SRXCLAV SRXSOC SRXPRTY MDTACK1 RXADDR4 RXSOC RXENB RXEMPTY RXPHYID3 RXPHYID2 RXPHYID1 RXPHYID0 RXPRTY RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1 RXDATA0 EMDATA31 EMDATA30 I/O Cell Type bidir bidir bidir bidir bidir in bidir bidir bidir tri-state tri-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir System Mode tri-state tri-state tri-state tri-state tri-state in out tri-state tri-state tri-state tri-state in out in bidir bidir bidir bidir in in in in in in in in in bidir bidir 175 173 171 169 167 165 164 162 160 158 157 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 Scan Bit # 174 172 170 168 166 enscan4 163 161 159 enscan6 enscan3 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 Output Enable enscan4 enscan4 enscan4 enscan4 enscan4 -- -- enscan4 enscan4 -- -- -- -- -- enscan3 enscan3 enscan3 enscan3 -- -- -- -- -- -- -- -- -- enscan5 enscan5 MOTOROLA MC92501 Data Sheet 4-5 MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name EMDATA29 EMDATA28 EMDATA27 EMDATA26 EMDATA25 EMDATA24 EMDATA23 EMDATA22 EMDATA21 EMDATA20 EMDATA19 EACEN EMWR EMDATA18 EMDATA17 EMDATA16 EMDATA15 EMDATA14 EMDATA13 EMDATA12 EMDATA11 EMDATA10 EMDATA9 EMDATA8 EMDATA7 EMDATA6 EMDATA5 EMDATA4 EMDATA3 I/O Cell Type bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir tri-state tri-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir System Mode bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir out out bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir 120 118 116 114 112 110 108 106 104 102 100 98 97 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 Scan Bit # 119 117 115 113 111 109 107 105 103 101 99 -- -- 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 Output Enable enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 -- -- enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 4-6 MC92501 Data Sheet MOTOROLA MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name EMDATA2 EMDATA1 EMDATA0 EMADD23 EMADD22 EMADD21 EMADD20 EMADD19 EMADD18 EMADD17 EMADD16 EMADD15 EMADD14 EMADD13 EMADD12 EMADD11 EMADD10 EMADD9 EMADD8 EMADD7 EMADD6 EMADD5 EMADD4 EMADD3 EMADD2 EMBSH0 EMBSH1 EMBSH2 EMBSH3 I/O Cell Type bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir tri-state tri-state tri-state tri-state System Mode bidir bidir bidir out out out out out out out out out out out out out out out out out out out out out out out out out out 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 13 12 11 Scan Bit # 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 -- -- -- -- Output Enable enscan5 enscan5 enscan5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOTOROLA MC92501 Data Sheet 4-7 MC92501 Table 4-1. MC92501 Boundary Scan Bit Definition (Continued) Signal Name EMBSL0 EMBSL1 EMBSL2 EMBSL3 ARST enscan1 enscan2 enscan3 enscan4 enscan5 enscan6 I/O Cell Type tri-state tri-state tri-state tri-state in (core macro) (core macro) (core macro) (core macro) (core macro) (core macro) System Mode out out out out in -- -- -- -- -- -- 10 9 8 7 6 5 4 3 2 1 0 Scan Bit # -- -- -- -- -- -- -- -- -- -- -- Output Enable -- -- -- -- -- -- -- -- -- -- -- 4-8 MC92501 Data Sheet MOTOROLA 5 Ordering Information Table 5-1. Ordering Information Part MC92501 Supply Voltage 3.3 V Package Type Glob-Top Ball Grid Array (GTBGA) Pin Count 256 Order Number MC92501GC MOTOROLA MC92501 Data Sheet 5-1 MC149570 5-2 MC92501 Data Sheet MOTOROLA Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including " Typicals" must be validated for each customer application by customer' technical experts. Motorola does not , s convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 MfaxTM : RMFAX0@email.sps.mot.com-- TOUCHTONE 1-602-244-6609 Motorola Fax Back System -- US & Canada ONLY 1-800-774-1848 -- http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Customer Focus Center: 1-800-521-6274 MC92501/D |
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